Hi There,
I'm Parv Rasadiya

i am

About Me

I'm PARV

VLSI Design & Verification Enthusiast

I am a dedicated VLSI engineer currently pursuing M.Tech at PDEU, with hands-on experience in FPGA development, IC layout design, and digital verification. I've gained valuable exposure through internships at SVNIT and Rhino Machines, and I'm actively involved in teaching as a Teaching Assistant. My interests lie in RTL design, physical design, and ASIC workflows. I enjoy solving real-world problems and bringing innovative ideas from concept to silicon.

phone : +91 63553 40719

email : work.parvrasadiya@gmail.com

place : Surat, Gujarat, India

Tools & Technologies

Industry-standard EDA platforms, semiconductor ecosystems & hardware tools I work with

Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo
Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo
Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo
Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo
Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo
Cadence logo
Synopsys logo
Siemens EDA / Mentor Graphics logo
NVIDIA logo
Intel logo
Arm logo
TSMC logo
AMD / Xilinx logo
Qualcomm logo
Applied Materials logo
Micron logo
Samsung logo

Skills & Abilities

Verilog 98%
SystemVerilog 91%
Python 85%
C 75%
Shell Scripting 87%
Cadence Virtuoso 95%
Xilinx Vivado 87%
Synopsys Verdi 80%
LTSpice 88%
MS Office Tools 96%

My Education

Education is not the learning of facts, but the training of the mind to think !

Pandit Deendayal Energy University- PDEU (Formerly PDPU), Gandhinagar

M.Tech in VLSI Design | CGPA : 9.5/10

2024-2026

Birla Vishvakarma Mahavidyalaya, Anand

B.Tech in Electronics Engineering

2020-2024 | Completed

Ashadeep IIT, Surat

HSC Science | GSEB

2018-2020 | Completed

Projects Made

Serial Communication Protocols

Designed and verified SPI and UART modules using Verilog. Verified using simulation and testbenches for serial communication integrity.

Sum of N Natural Numbers on FPGA

Used Verilog to compute and display the sum of N natural numbers on a 3-digit 7-segment display using FSM and Double Dabble algorithm. Implemented on Artix-7 using Xilinx Vivado.

Binary to Gray Converter (4T XOR)

Designed a compact XOR gate using 4 transistors in Cadence Virtuoso and implemented a Binary to Gray code converter using it. Complete layout designed and tested.

IOT base Smart Car Parking System

An IoT-based parking system is a centralized management that enables drivers to search for and reserve a parking spot remotely through their smartphones.

4x4X4 LED Cube using arduino

4x4x4 LED Cube has 64 LEDs. These are all wired to a Arduino Uno. An Arduino is a single-board microcontroller, a 3D LED cube can be used for displaying various patterns or structures in 3 dimensional plane.

Experience

SVNIT & SUCHI Semicon

June 2025 – July 2025 | VLSI Training Program

Completed a 5-week hands-on training in VLSI design, semiconductor fabrication, cleanroom processes, and IC packaging techniques.

Teaching Assistant – PDEU

Aug 2024 – Present

Assisting professors in lecture preparation, grading, and mentoring students in VLSI and digital design subjects.

Publicity Head – UDAAN'24

April 2024 | Birla Vishvakarma Mahavidyalaya

Led the publicity team for UDAAN'24, BVM's 3-day techno-cultural fest. Managed promotions, coordinated volunteers, and drove student engagement.

Rhino Machines Pvt. Ltd., Anand

Jan 2024 – May 2024 | Internship

Worked on a PLC-based industrial weighing system. Integrated hardware into automation systems and collaborated with the automation team.

ACDC Tech, Surat

June 2023 – July 2023 | Internship

Contributed to PCB design, component footprint verification, soldering, and R&D testing of hardware modules in the electronics lab.

Awards & Certifications

“Each certificate is not just paper — it’s proof of passion, persistence, and purpose.”

Advanced Verification and UVM

Advanced Verification and UVM

EDA Workshop – Micron ICONN

SystemVerilog for Design and Verification v21.10

Cadence Layout Training

Verilog Language and Application v28.0

EDA Workshop – Synopsys EDA Tools

RTL to GDSII using Synopsys EDA Tools

Suchi Semicon Training

5-Week Training Program – Suchi Semicon @ SVNIT

Cadence RTL to GDSII Flow v6.0

Cadence RTL to GDSII Flow v6.0

Fundamentals of VLSI

Fundamentals of VLSI

OCI Generative AI Professional

OCI Generative AI Professional

TCS iON Career Edge - Young Professional

TCS iON Career Edge - Young Professional

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